Gross Die Estimator´s caveats for ASIC floorplanning

Floorplanning is essential elements in ASIC chip design. As design complexity increase with various IP packaging on single die, a good floorplanning will help to drive the product cost lower as well as reduce the design hiccup. For optimum product cost estimation, die count estimation is essential element based on floorplanning feedback. Gross Die Estimator is the common equation used to derive the product cost estimation in new product planning phase. The intend of this paper is to analyze the prior art to ASIC floorplanning from die analysis perspective, Gross Die Estimator and the caveats of gross die estimator usage.