Improvement of the surface quality of polished InP wafers

Indium phosphide wafers are often used as epi ready wafers. Especially for MOVPE grown structures, the electrical conduction at the interface between the semi insulating substrate and the epitaxial layer is a crucial issue. Silicon contamination is the origin of the interface conduction. We demonstrate that TOF-SIMS is a very powerful technique to characterise the surface and investigate any contamination at the interface such as the low silicon content. TOF-SIMS analysis has been performed after various chemical preparations. It allows us to detect all the elements and molecules present on the surface, even in very low concentration (10¹⁰ at/cm²). Thanks to these results, we are now able to produce wafers with a very clean surface in a reproducible way. Furthermore, the TOF-SIMS results explain the conductive buffer layer obtained by MOCVD epitaxy