Full-custom design of low leakage data preserving ground gated 6T SRAM cells to facilitate single-ended write operations

An asymmetrically ground-gated six-transistor (6T) SRAM circuit is presented in this paper for providing a low leakage data preserving SLEEP mode. By employing multiple write assist techniques, the write margin is enhanced by up to 2.73x and the write access time is reduced by up to 57.45% as compared with a previously published asymmetrically ground-gated 6T SRAM circuit in a TSMC 65nm CMOS technology. Furthermore, the new ground-gated 6T memory circuit enhances the data stability by 2.09x and reduces the leakage power consumption by 58.55% as compared to a ground-gated memory array with conventional 6T SRAM cells. A design methodology is presented to optimize the asymmetrically ground-gated 6T SRAM circuits for achieving the highest overall electrical quality.