Low-power variation-aware flip flop

Parameter variations in nanometer process technology are one of the major design challenges. They cause to be increased delay on the critical path and to change the logic level of internal nodes. The basic concept to solve these problems at the circuit level, design-for-variability (DFV), is to add error handling circuits at the conventional circuits so that they are robust to nanometer related variations. The state-of-the-art variation-aware flip flops are mainly evolved from aggressive DVFS (dynamic voltage and frequency scaling) -based low-power application systems which handle errors caused from the scaled supply voltage. They only detect the timing errors and cannot correct the errors. We propose a variation-aware flip flop which can detect and correct the timing error efficiently. The experimental results show that the proposed variation-aware flip flop is more robust and lower power than the existing approaches.