Title :
A general purpose neuro-image processor architecture
Author :
Han, Gunhee ; Sanchez-Sinencio, Edgar
Author_Institution :
Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
Abstract :
A general purpose neuro-image processor architecture based on the Multiplexing Neuron Array (MNA) is proposed. It is a pseudo parallel matrix-vector multiplier. The proposed architecture can process not only vector signals but two dimensional signals as well, so various types of neural networks or image processing paradigm can be implemented without any hardware modification. The major advantage is an unlimited expansion capability due to simple routings between processing elements. The architecture can be implemented with any discrete-time system, i.e., digital system, Switched-Capacitor, Switched-Current. For illustration, a multilayer perceptron network and recurrent network are implemented with fabricated Switched-Capacitor CMOS chips
Keywords :
CMOS integrated circuits; digital signal processing chips; image processing; multilayer perceptrons; multiplying circuits; neural chips; recurrent neural nets; switched capacitor networks; switched current circuits; vector processor systems; CMOS chips; digital system; discrete-time system; expansion capability; image processing paradigm; multilayer perceptron network; multiplexing neuron array; neuro-image processor architecture; processing elements; pseudo parallel matrix-vector multiplier; recurrent network; switched-capacitor system; switched-current system; two dimensional signals; vector signals; Application software; Cellular neural networks; Computer architecture; Concurrent computing; Image processing; Neural networks; Neuroimaging; Neurons; Parallel processing; Signal processing;
Conference_Titel :
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location :
Atlanta, GA
Print_ISBN :
0-7803-3073-0
DOI :
10.1109/ISCAS.1996.541641
