The stretched-hypercube: a VLSI efficient network topology

In this paper, we introduce a new class of interconnection networks for multiprocessor systems which we refer to as stretched-hypercubes, or shortly the stretched-cube networks. These networks are obtained by replacing an edge of the well-known hypercube network with an array of processors. Two interesting features of the proposed topology are its area-efficient VLSI layout and superior scalability over the traditional hypercube network. Some topological properties of the proposed network are studied. In addition, an area-efficient VLSI layout for the stretched-cube is suggested and some comparisons between the proposed network and previously studied networks such as the star and hypercube are conducted.