Title :
Design of universal pipelining discrete time cellular neural network by PARTHENON
Author :
Numata, Hajime ; Ikegami, Munematsu ; Tanaka, Mamoru
Author_Institution :
Dept. of Electr. Eng., Sophia Univ., Tokyo, Japan
Abstract :
We have developed a universal chip for image processing by Discrete Time Cellular Neural Network (DTCNN) algorithm. We propose a ring-connected processor array architecture called pipelining DTCNN by which the convergence of output image is fast and done efficiently. In this paper, we introduce the hardware implementation of image halftoning by DTCNN with MOSIS, and the analysis of efficiency of pipelining DTCNN
Keywords :
cellular neural nets; discrete time systems; image processing; neural chips; neural net architecture; pipeline processing; MOSIS hardware; PARTHENON; algorithm; convergence; design; discrete time cellular neural network; efficiency; image halftoning; image processing; pipelining DTCNN; ring-connected processor array architecture; universal chip; Cellular neural networks; Computer architecture; Convergence; Electronic mail; Hardware; Image processing; Neurons; Nonlinear distortion; Pipeline processing; Pixel;
Conference_Titel :
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location :
Atlanta, GA
Print_ISBN :
0-7803-3073-0
DOI :
10.1109/ISCAS.1996.541661
