Digital comb filter implementation for the IIΔΣ A/D converter

This paper describes a topology for the design and implementation of decimation comb filters used in the parallel delta-sigma (IIΔΣ) A/D converter. The comb filter implementation presented here avoids any multibit digital multiplication and, by translating some of the processing through the downsampler to lower clock speeds, an area efficient and low power implementation is realized. The circuit implementation uses true single phase clocking, antiphase clocking and pipelining to obtain the necessary speed. A prototype of a 22-bit, 418-tap comb filter was designed, fabricated and tested in a 2 μm p-well CMOS process for use in an eight-channel, 15-bit IIΔΣ A/D converter operating at a sampling rate of 20 MHz. The testing results showed that the filter worked as expected