Multiply-accumulate instruction set extension in a soft-core RISC Processor

Application Specific Instruction Set Processor (ASIP) design is known to offer optimum performance and flexibility in a processor performance although with limited application. Implementing the processor on Field Programmable Gate Array (FPGA) further extend the opportunity to reconfigure the architecture instantaneously. In this paper, the instruction set extension approach is implemented on a simple 8-bit soft-core RISC processor to enhance the processor capability by adding new instruction set that can allow it to perform basic digital signal processing (DSP) algorithm. Creation of new instruction set is achieved by modifying the processor´s architecture using Hardware Description Language (HDL). For verification purposes, a multiply-accumulate (MAC) instruction is created in addition to existing RISC instructions. The MAC instruction set, which is the fundamental operation of DSP algorithms, involved 8×8 bit multiplication and the accumulation result is stored in two 8-bit register-pair. The new instruction set must adhere to the current instruction set architecture (ISA) in order to ensure the new instruction is fully compatible to the existing architecture. The instruction is successfully tested through execution of RISC processor on FPGA chip and correct output has been observed from the MAC instruction. The results show that through instruction set extension approach, a low-end RISC processor is capable to execute more complex instructions just by reconfiguring the instruction set to match the specific system requirement. The approach also offers flexibility in instruction extension and the resource is only limited to the constraint of the FPGA chip where the processor resides.