Title :
Design of low power, low jitter DLL tested at all five corners to avoid false locking
Author :
Raghav, Himadri Singh ; Maheshwari, Shishir ; Srinivasarao, M. ; Singh, Bhanu Pratap
Author_Institution :
Fac. of Eng. & Technol. (FET), Mody Inst. of Technol. & Sci. (MITS), Lakshmangarh, India
Abstract :
A modified Phase Selection Circuit, a modified Phase Frequency Detector and a modified Voltage Controlled Delay Line is proposed to improve the Delay Locked Loops (DLL) locking time, lock range and the jitter performance. Also the DLL presented in this paper has a wide-range frequency operation. A modified Phase Selection circuit is designed in order to operate DLL over wide frequency range and completely solve the false locking problem. Also a Modified Phase Frequency detector circuit has been designed to reduce the phase error as well as dead-zone situation. The proposed DLL design is simulated in Cadence Spectre using TSMC 180nm CMOS Technology and 1.8V power supply voltage operate correctly when the input clock frequency is changed from 84 to 800MHz and generate ten-phase clocks within just one clock cycle. The simulation is performed for all five process corners. The DLL consumes maximum power of 6.85mW at 800MHz working at FF corner, whereas, the maximum peak-to-peak jitter is 4ps at 84MHz working at FS corner. Both maximum power and jitter is measured at temperature and voltage of -40°C and 1.98V.
Keywords :
CMOS integrated circuits; delay lines; delay lock loops; jitter; low-power electronics; phase detectors; Cadence Spectre; FF corner; FS corner; TSMC CMOS technology; clock cycle; dead-zone situation; delay locked loop locking time; false locking avoidance; false locking problem; frequency 84 MHz to 800 MHz; jitter performance; lock range; low power low jitter DLL design; modified phase frequency detector circuit; modified phase selection circuit; modified voltage controlled delay line; phase error reduction; power 6.85 mW; size 180 nm; temperature -40 degC; voltage 1.8 V; voltage 1.98 V; Clocks; Delay; Image edge detection; Jitter; Multiplexing; Phase frequency detector; Voltage control; dead-zone; delay locked loop; false locking; peak-to-peak jitter; phase error; phase frequency detector; phase selection circuit;
Conference_Titel :
Semiconductor Electronics (ICSE), 2012 10th IEEE International Conference on
Conference_Location :
Kuala Lumpur
Print_ISBN :
978-1-4673-2395-6
Electronic_ISBN :
978-1-4673-2394-9
DOI :
10.1109/SMElec.2012.6417201
