Design of low power, low jitter DLL tested at all five corners to avoid false locking

A modified Phase Selection Circuit, a modified Phase Frequency Detector and a modified Voltage Controlled Delay Line is proposed to improve the Delay Locked Loops (DLL) locking time, lock range and the jitter performance. Also the DLL presented in this paper has a wide-range frequency operation. A modified Phase Selection circuit is designed in order to operate DLL over wide frequency range and completely solve the false locking problem. Also a Modified Phase Frequency detector circuit has been designed to reduce the phase error as well as dead-zone situation. The proposed DLL design is simulated in Cadence Spectre using TSMC 180nm CMOS Technology and 1.8V power supply voltage operate correctly when the input clock frequency is changed from 84 to 800MHz and generate ten-phase clocks within just one clock cycle. The simulation is performed for all five process corners. The DLL consumes maximum power of 6.85mW at 800MHz working at FF corner, whereas, the maximum peak-to-peak jitter is 4ps at 84MHz working at FS corner. Both maximum power and jitter is measured at temperature and voltage of -40°C and 1.98V.