Title :
Implementation of one bit delay 2-D IIR digital filters
Author :
Hu, Z. ; King, G. ; Al-Dabass, D.
Author_Institution :
Syst. Eng. Res. Centre, Southampton Inst., UK
Abstract :
A novel systolic architecture for implementing bit-level 2-D IIR filters is presented which solves the basic problem of latency in the feed back loop. The design results in a throughput rate of one sample every clock cycle. The simple modular structure leads to efficient an VLSI implementation. The conventional pipelined shift and add multiplier array is fully described
Keywords :
IIR filters; VLSI; delay circuits; pipeline processing; systolic arrays; two-dimensional digital filters; VLSI; add multiplier array; bit-level processing; design; feedback loop; latency; modular structure; one bit delay 2D IIR digital filter; pipelined shift; systolic architecture; throughput rate; Circuits; Clocks; Delay; Digital filters; Feedback loop; Feeds; Finite impulse response filter; Hardware; IIR filters; Pipeline processing;
Conference_Titel :
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location :
Atlanta, GA
Print_ISBN :
0-7803-3073-0
DOI :
10.1109/ISCAS.1996.541753
