DocumentCode :
3026348
Title :
Task-binding based branch-and-bound algorithm for NoC mapping
Author :
Liyang Zhou ; Ming´e Jing ; Liulin Zhong ; Zhiyi Yu ; Xiaoyang Zeng
Author_Institution :
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
fYear :
2012
fDate :
20-23 May 2012
Firstpage :
648
Lastpage :
651
Abstract :
Network-on-Chip (NoC) architecture is drawing intensive attention since it promises to maintain high performance in handling complex communication issues as the number of on-chip components increases. Mapping a given application onto the multi-core processors on NoC to obtain a high performance is a significant challenge. In this paper, we propose an optimized branch-and-bound (B&B) mapping algorithm to reduce the communication energy or improve the mapping efficiency by binding the tasks together when they have a large communication volume. Experimental results show that the proposed algorithm can achieve high performance in a short time compared with the traditional algorithm. For example, when mapping 64 tasks onto an 8×8 NoC system, with the approximate run time, 14.72% and 64.11% average energy consumption is saved compared with the original B&B and simulated annealing (SA) algorithms, respectively.
Keywords :
logic design; network-on-chip; simulated annealing; tree searching; NoC mapping; NoC system; communication energy; energy consumption; mapping efficiency; multicore processors; network-on-chip architecture; on-chip components; optimized branch-and-bound mapping algorithm; simulated annealing algorithms; task-binding based branch-and-bound algorithm; Algorithm design and analysis; Approximation algorithms; Benchmark testing; Energy consumption; Heuristic algorithms; Program processors; Runtime;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), 2012 IEEE International Symposium on
Conference_Location :
Seoul
ISSN :
0271-4302
Print_ISBN :
978-1-4673-0218-0
Type :
conf
DOI :
10.1109/ISCAS.2012.6272115
Filename :
6272115
Link To Document :
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