Title :
Design of low power UWB LNA for frequency 3.1–5 GHz in 0.18 μm CMOS technology
Author :
Sahu, Akanksha ; Sau, Paresh Chandra ; Kalra, Dheeraj
Author_Institution :
Dept. of ECE, G.L.A. Univ., Mathura, India
Abstract :
This paper present 3.1-5 GHz low noise amplifier (LNA) for UWB receivers. In this proposed circuit, cascade and cascode topology with modified input matching are designed. Proposed LNA achieves a maximum gain 22.252 dB, a noise figure 0.921-1.646 dB with a wide input matching. The power consumption is low under a 1.6-V dc power supply. The proposed UWB LNA is implemented using 0.18 μm based CMOS technology under TSMC.
Keywords :
CMOS integrated circuits; MMIC amplifiers; low noise amplifiers; low-power electronics; radio receivers; ultra wideband technology; CMOS technology; UWB LNA; UWB receivers; cascade topology; cascode topology; frequency 3.1 GHz to 5 GHz; gain 22.252 dB; low noise amplifier; modified input matching; noise figure 0.921 dB to 1.646 dB; size 0.18 mum; voltage 1.6 V; CMOS integrated circuits; Gain; Impedance matching; Logic gates; Noise figure; Topology; Transistors; CMOS; LNA; NF; UWB;
Conference_Titel :
Computing, Communication & Automation (ICCCA), 2015 International Conference on
Conference_Location :
Noida
Print_ISBN :
978-1-4799-8889-1
DOI :
10.1109/CCAA.2015.7148371
