Discrete space continuous time 2D delay block using 2D all-pass frequency planar networks

A two-dimensional (2D) space-time (ST) delay operator D_2D^ST [·] and a novel discrete-space-continuous-time (DSCT) CMOS VLSI implementation at radio frequency (RF) is proposed. The proposed delay operator is able to delay 2D ST antenna array signals along space and time and can be used as a building block in 2D ST array processing algorithms. A 2D non-separable DSCT transfer function (TF), Φ_App (z_x, s_ct) is used to approximate the ideal 2D ST delay represented by the 2D TF equation. A passive frequency planar transformation followed by bilinear transform along spatial dimension is used to derive Φ_App (z_x, s_ct) starting from a 1D passive all-pass prototype. The 2D delay D_2D^ST [·] is proposed to be realized using an array of identical analog modules (AMs). A CMOS VLSI circuit operating at RF is proposed for each AM. Magnitude and phase frequency responses of a single AM operating at 1 GHz is obtained using 65 nm TSMC CMOS simulations in Cadence and compared with the theoretical responses. The 2D phase frequency response of D_2D^ST [·] is obtained using the CMOS simulated response of a single AM.