A 1.8V–0.18µm CMOS lock-in amplifier for portable applications

Author

Maya-Hernández, P.M. ; Sanz-Pascual, M.T. ; Calvo, B.

Author_Institution

Electron. Dept., Inst. Nac. de Astrofis., Tonantzintla, Mexico

fYear

2012

fDate

20-23 May 2012

Firstpage

668

Lastpage

671

Abstract

This paper presents a new analog lock-in amplifier designed in a 0.18μm CMOS process with a single supply voltage of 1.8V. The proposed architecture, which recovers the signal of interest from noisy environments with errors below 4% for noise signals of the same amplitude as the signal of interest, is suitable for portable applications thanks to its reduced power consumption and single-supply voltage operation. Post-layout simulation results show a variable DC gain ranging from 20 to 40dB, input-referred noise of 28.3μmV_rms, power consumption of 351.4μW and area of (253×52)μm².

Keywords

CMOS analogue integrated circuits; amplifiers; integrated circuit design; integrated circuit noise; CMOS process; analog lock-in amplifier; gain 20 dB to 40 dB; input-referred noise; noise signal environment; portable application; post-layout simulation; power 51.4 muW; power consumption; single-supply voltage operation; size 0.18 mum; variable DC gain; voltage 1.8 V; voltage 28.3 muV; Gain; Mixers; Noise; Power demand; Resistors; Sensors; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2012 IEEE International Symposium on

Conference_Location

Seoul

ISSN

0271-4302

Print_ISBN

978-1-4673-0218-0

Type

conf

DOI

10.1109/ISCAS.2012.6272121

Filename

6272121