DocumentCode
302653
Title
VLSI implementation of vector quantization using distributed arithmetic
Author
Cao, H.Q. ; Li, Weiping
Author_Institution
Dept. of Comput. Sci. & Electr. Eng., Lehigh Univ., Bethlehem, PA, USA
Volume
2
fYear
1996
fDate
12-15 May 1996
Firstpage
668
Abstract
A new full search vector quantization (VQ) encoding algorithm under mean square error (MSE) criterion is introduced using adaptive distributed arithmetic (DA). The MSE computations in VQ can be converted to inner product computations which can be efficiently carried out using DA. However, the conventional wisdom of storing all possible combinations of codevectors requires an extremely large memory which makes DA unrealistic for VQ. In the new algorithm, the combinations of the input vector are stored in a memory and the codevectors are used as addresses. This dramatically reduces the memory requirement of VQ using DA so that a VLSI design becomes possible. A VLSI structure for the implementation of this distributed arithmetic VQ (DAVQ) algorithm is proposed. It is estimated that a single chip using 1.2 μ CMOS technology can perform a real-time exhaustive search VQ of 256 16-dimensional codevectors for video compression of CIF format at 30 frames/second
Keywords
CMOS digital integrated circuits; VLSI; determinants; digital arithmetic; digital signal processing chips; vector quantisation; 1.2 micron; CIF format; CMOS chip; VLSI; distributed arithmetic; full search vector quantization encoding algorithm; inner product computation; mean square error; vector quantization; video compression; CMOS technology; Costs; Digital arithmetic; Encoding; Mean square error methods; Silicon; Space technology; Throughput; Vector quantization; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location
Atlanta, GA
Print_ISBN
0-7803-3073-0
Type
conf
DOI
10.1109/ISCAS.1996.541813
Filename
541813
Link To Document