A multi-path high speed Viterbi decoder

Author

Obeid, Abdulfattah M. ; Garcia, Alberto ; Petrov, Mihail ; Glesner, Manfred

Author_Institution

Inst. for Microelectron. Syst., Darmstadt Univ. of Technol., Germany

Volume

3

fYear

2003

fDate

14-17 Dec. 2003

Firstpage

1160

Abstract

In this work, a multi-path Trace-Back Viterbi decoder architecture is proposed. It offers almost ideal error correction quality with relatively low overhead. Moreover, a technique that enhances the error correction quality of Register-Exchange decoders as well as a normalization technique that saves considerable area are introduced. The proposed techniques can be utilized for efficient realizations of high speed systolic as well as low speed sequential Viterbi decoder architectures.

Keywords

Viterbi decoding; error correction; sequential circuits; systolic arrays; current best state; high speed systolic decoder; ideal error correction quality; multipath high speed Viterbi decoder; normalization technique; punctured coding; register-exchange decoders; relatively low overhead; sequential realizations; trace-back Viterbi decoder; Costs; Decoding; Energy consumption; Error correction; Microelectronics; Registers; Signal synthesis; Signal to noise ratio; Transceivers; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on

Print_ISBN

0-7803-8163-7

Type

conf

DOI

10.1109/ICECS.2003.1301718

Filename

1301718