Title :
A novel high-speed counter with counting rate independent of the counter´s length
Author :
Kakarountas, A.P. ; Theodoridis, G. ; Papadomanolakis, K.S. ; Goutis, C.E.
Author_Institution :
Dept. of Electr. & Comput. Eng., Patras Univ., Greece
Abstract :
Counters are among the basic blocks in every digital system. We propose a novel high-speed counter with a constant counting rate, independent of its length. Exploiting special features of the binary arithmetic system and adopting prescaling techniques, a segmented counter architecture is introduced. Particularly, to realize a counter of any length properly, two designed modules of four-bit counter are used in a systolic manner. The counting rate is bounded by the delay of two basic gates of three inputs plus the delay of a T F/F. In AMS 0.6 μm technology a maximum of 430 MHz counting frequency is achieved.
Keywords :
CMOS logic circuits; VLSI; counting circuits; hardware description languages; high-speed integrated circuits; logic CAD; logic gates; prescalers; Boolean simplifications; VHDL; binary arithmetic system; cascaded two-input AND gates; constant counting rate; four-bit counter; high-speed VLSI design; high-speed counter; length independent counting; prescaling; segmented counter; Arithmetic; Clocks; Counting circuits; Delay; Digital systems; Frequency synthesizers; Physics computing; Time measurement; Velocity measurement; Very large scale integration;
Conference_Titel :
Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on
Print_ISBN :
0-7803-8163-7
DOI :
10.1109/ICECS.2003.1301719
