DocumentCode
3026634
Title
Double-rail encoded self-timed adder with matched delays
Author
Amin, Aluueldin ; Maadi, F.
Author_Institution
Comput. Eng. Dept., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia
Volume
3
fYear
2003
fDate
14-17 Dec. 2003
Firstpage
1172
Abstract
An efficient self-timed adder with low area overhead and efficient acknowledge slack time is proposed. The adder uses double-rail encoding of the carry signals as well as process-tracking matching delays to guarantee proper generation of the completion signal.
Keywords
SPICE; adders; carry logic; delays; SPICE simulations; arithmetic processors; carry propagation; carry signals; completion signal generation; double-rail encoding; efficient acknowledge slack time; low area overhead; process-tracking matching delays; self-timed adder; worst case delay; Added delay; Adders; Circuits; Delay effects; Encoding; Optical computing; Petroleum; Propagation delay; Signal generators; Signal processing;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on
Print_ISBN
0-7803-8163-7
Type
conf
DOI
10.1109/ICECS.2003.1301721
Filename
1301721
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