Title :
Assessing merged DRAM/logic technology
Author :
Kim, Yong-Bin ; Chen, Tom
Author_Institution :
Eng. Syst. Lab., Fort Collins, CO, USA
Abstract :
This paper describes the impact of the DRAM process on the logic circuit performance of Memory/Logic Merged Integrated Circuits and the alternative circuit design technology to offset the performance penalty. Three state-of-the-art logic processes (0.5 μm, 0.6 μm, and 0.8 μm) and two state-of-the-art DRAM (64 Mb and 256 Mb) processes have been selected for the study. The simulation results show that the logic circuit performance is degraded by about 22% on the DRAM process including increased interconnect delay due to less interconnect layers available in the DRAM process. The silicon area increased up to 80% depending on the number of nets and components when implementing the logic circuit in the DRAM process
Keywords :
CMOS logic circuits; CMOS memory circuits; DRAM chips; circuit analysis computing; delays; integrated circuit layout; logic design; network routing; 0.5 to 0.8 mum; 256 Mbit; 64 Mbit; CMOS circuit; circuit design technology; interconnect delay; logic circuit performance; logic circuit performance degradation; merged DRAM/logic technology; performance penalty; routing area penalty; silicon area increase; simulation results; Circuit simulation; Circuit synthesis; Degradation; Delay; Integrated circuit interconnections; Integrated circuit technology; Logic circuits; Logic design; Random access memory; Silicon;
Conference_Titel :
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location :
Atlanta, GA
Print_ISBN :
0-7803-3073-0
DOI :
10.1109/ISCAS.1996.541917
