DocumentCode
302705
Title
Clock skew on DRAM/logic merged technology based systems
Author
Kim, Yong-Bin ; Chen, Tom
Author_Institution
Lab. of Eng. Syst., Hewlett-Packard Co., Fort Collins, CO, USA
Volume
4
fYear
1996
fDate
12-15 May 1996
Firstpage
141
Abstract
This paper describes the clock skew estimations considering all the possible clock skew factors on DRAM/Logic merged systems. The clock skew difference between a standard logic chip and DRAM/Logic merged chips has been estimated as 521 ps for 4×4 cm2 die size. The relationship between clock skew and die size on DRAM/Logic merged systems has been obtained along with the maximum operating clock frequency assuming clock skew can take up to 15% of the total clock cycle on such a large chip
Keywords
DRAM chips; clocks; delays; integrated logic circuits; logic design; DRAM/logic merged technology; RC delay; buffered H-tree clock distribution; clock skew estimation; clock skew factors; die size; maximum operating clock frequency; Bandwidth; Clocks; Delay; Integrated circuit interconnections; Logic arrays; Microprocessors; Power dissipation; Power system interconnection; Random access memory; Systems engineering and theory;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location
Atlanta, GA
Print_ISBN
0-7803-3073-0
Type
conf
DOI
10.1109/ISCAS.1996.541919
Filename
541919
Link To Document