A novel high speed low skew clock distribution scheme in 0.8 micron CMOS

This paper presents a novel clock distribution scheme to achieve low skew in high-speed VLSI systems. The method was devised to solve the problem of distributing a 1.0 GHz clock along a 1.0 Gbps 10-channel wide PECL to CMOS interface circuit. The differential clock signals are distributed along a lossy transmission line which is connected between the differential input stage of an amplifier and the diode-connected load of the differential amplifier, forming a distributed differential amplifier which is in effect the clock distribution circuitry. This scheme results in a simulated skew of less than 20.0 ps across 3600 μm. Although the targeted clock frequency is very close to the performance limits of the technology, our approach increases the operating frequency of practical VLSI systems in 0.8 μm CMOS technology