DocumentCode
302711
Title
Design of parallel signal processing system for real-time SHD image processing
Author
Nomura, Mitsuru ; Sawabe, Tomoko ; Fujii, Tetsurou ; Ono, Sadayasu
Author_Institution
NTT Optical Network Syst. Labs., Kanagawa, Japan
Volume
4
fYear
1996
fDate
12-15 May 1996
Firstpage
172
Abstract
This paper describes a parallel signal processing system architecture for Super High Definition (SHD) image processing. A new communication processor called “Dataway Processor” has been developed to achieve high speed inter-processor communication and image data transfer. A prototype system, consisting of a 32-node processing engine, an SHD image display interface, and an ATM network interface, is currently under development
Keywords
image processing; parallel architectures; real-time systems; ATM network interface; Dataway Processor; communication processor; high speed inter-processor communication; image data transfer; image display interface; parallel signal processing system architecture; real-time SHD image processing; Biomedical signal processing; Communication system control; Digital signal processing; Engines; Image processing; Optical signal processing; Real time systems; Routing; Signal design; Signal processing;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location
Atlanta, GA
Print_ISBN
0-7803-3073-0
Type
conf
DOI
10.1109/ISCAS.1996.541927
Filename
541927
Link To Document