Title :
Quasi delay-insensitive bus for fully asynchronous systems
Author :
Molina, Pedro A. ; Cheung, P.Y.K. ; Bormann, David S.
Author_Institution :
Dept. of Electr. & Electron. Eng., Imperial Coll. of Sci., Technol. & Med., London, UK
Abstract :
In this paper the design of a dual rail asynchronous system bus is presented. Buses are generally avoided in asynchronous design because it is difficult to meet the isochronic fork assumption on heavily loaded wires. Our bus design avoids this assumption and provides a quasi delay-insensitive solution. The proposed solution makes a system modular and scaleable by guaranteeing that the complexity of the system grows linearly with each module added
Keywords :
asynchronous circuits; delays; system buses; asynchronous system; dual rail bus; heavily loaded wire; isochronic fork; quasi delay-insensitive bus; scaleable modular system; Asynchronous circuits; Clocks; Delay; Energy consumption; Integrated circuit interconnections; Logic circuits; Signal design; Timing; Very large scale integration; Wires;
Conference_Titel :
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location :
Atlanta, GA
Print_ISBN :
0-7803-3073-0
DOI :
10.1109/ISCAS.1996.541932
