Design of repairable and fully testable folded PLAs

The yield of ICs is crucial to the commercial success of their manufacture. One practical solution to the low yield problem is the use of fault-tolerant design. A fault diagnosable and repairable PLA design has been proposed to detect, locate, and repair faults, and has led to a significant yield improvement. An alternated defect-tolerant design of PLAs with folding technique is presented to further improve chip yield. The proposed design achieves full diagnosability of stuck-at, bridging, and crosspoint faults during the manufacturing process, and provides full testability after the chip is packaged