Neuron-MOS correlator based on Manhattan distance computation for event recognition hardware

Author

Konda, M. ; Shibata, Tadashi ; Ohm, Tadahiro

Author_Institution

Dept. of Electron. Eng., Tohoku Univ., Sendai, Japan

Volume

4

fYear

1996

fDate

12-15 May 1996

Firstpage

217

Abstract

A minimum-distance-vector fully-parallel-search hardware has been developed based on neuron-MOS (νMOS) technology for use in real-time event recognition system. The distance calculation as well as the minimum distance search are conducted based on the voltage-mode operation principle of νMOS circuitry, thus enabling fast operation under relatively low power operation. The circuit operation has been demonstrated by HSPICE simulation and test circuits fabricated by a double-poly CMOS process with 3-μm layout rules

Keywords

CMOS integrated circuits; correlators; neural chips; pattern recognition; real-time systems; 3 micron; HSPICE simulation; Manhattan distance computation; double-poly CMOS process; low power operation; minimum-distance-vector fully-parallel-search; neuron-MOS correlator; real-time event recognition hardware; voltage-mode operation; Analog computers; CMOS process; Circuit simulation; Circuit testing; Correlators; Hardware; Intelligent systems; MOS devices; Parallel architectures; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on

Conference_Location

Atlanta, GA

Print_ISBN

0-7803-3073-0

Type

conf

DOI

10.1109/ISCAS.1996.541939

Filename

541939