A 12-bit, 270MS/s pipelined ADC with SHA-eliminating front end

Author

Wang, Xuan ; Yang, Changyi ; Zhao, Xiaoxiao ; Wu, Chao ; Li, Fule ; Wang, Zhihua ; Wu, Bin

Author_Institution

Inst. of Microelectron., Tsinghua Univ., Beijing, China

fYear

2012

fDate

20-23 May 2012

Firstpage

798

Lastpage

801

Abstract

This paper presents a 12-bit 270MS/s pipelined analog-to-digital converter (ADC) without employing a front-end sample-and-hold amplifier. A novel strategy is established to diminish the aperture error while maintaining both the original tracking time and amplifying time of multiplying digital-to-analog converter (MDAC). It matches the signal paths between comparators and MDAC in the first stage by using proper timing sequence and high-speed dynamic comparators. The measurement results show 63.7dB SNR and 76.1dBc SFDR at 120.1MHz input frequency while the chip´s total power dissipation is 250mW (excluding LVDS drivers) at 1.2V supply. The ADC core occupies 1.7mm² and is implemented in a 130nm CMOS process.

Keywords

CMOS integrated circuits; analogue-digital conversion; comparators (circuits); CMOS process; SHA-eliminating front end; aperture error; frequency 120.1 MHz; high-speed dynamic comparator; multiplying digital-to-analog converter; pipelined ADC; pipelined analog-to-digital converter; power 250 mW; size 130 nm; timing sequence; voltage 1.2 V; word length 12 bit; Apertures; Bandwidth; CMOS integrated circuits; Frequency measurement; Power demand; Signal to noise ratio; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2012 IEEE International Symposium on

Conference_Location

Seoul

ISSN

0271-4302

Print_ISBN

978-1-4673-0218-0

Type

conf

DOI

10.1109/ISCAS.2012.6272160

Filename

6272160