DocumentCode
3027241
Title
Novel overshoot cancellation in comparator-based pipelined ADC
Author
Tang, Xian ; Pun, Kong-Pang
Author_Institution
Dept. of Electron. Eng., Chinese Univ. of Hong Kong, Hong Kong, China
fYear
2012
fDate
20-23 May 2012
Firstpage
806
Lastpage
809
Abstract
In this paper, a new overshoot cancellation method is presented for comparator-based pipelined ADCs. By introducing charging and discharging operations in two adjacent stages, the large overshoot in each stage can be either tolerated as sub-ADC error or cancelled out with each other. Applying this concept, a 10-bit pipelined ADC has been designed and simulated in a 0.18-μm CMOS process. It achieves 57.2dB SNDR at 20MS/s and consumes 2.6mW under 1.8 V supply, resulting in an ENOB of 9.2-bit and an FOM of 0.221 pJ/Conv.-step.
Keywords
CMOS digital integrated circuits; analogue-digital conversion; comparators (circuits); CMOS process; ENOB; FOM; SNDR; adjacent stages; comparator-based pipelined ADC; discharging operations; noise figure 57.2 dB; overshoot cancellation method; power 2.6 mW; size 0.18 mum; subADC error; voltage 1.8 V; word length 10 bit; word length 9.2 bit; CMOS integrated circuits; CMOS technology; Capacitors; Delay; Educational institutions; Quantization; Topology;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), 2012 IEEE International Symposium on
Conference_Location
Seoul
ISSN
0271-4302
Print_ISBN
978-1-4673-0218-0
Type
conf
DOI
10.1109/ISCAS.2012.6272162
Filename
6272162
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