DocumentCode
302725
Title
An analytical delay model for RLC interconnects
Author
Kahng, Andrew B. ; Muddu, Sudhakar
Author_Institution
Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Volume
4
fYear
1996
fDate
12-15 May 1996
Firstpage
237
Abstract
We develop an analytical delay model based on first and second moments to incorporate inductance effects into the delay estimate for interconnection lines. Delay estimates using our analytical model are within 15% of SPICE-computed delay across a wide range of interconnect parameter values. We also extend our delay model for estimation of source-sink delays in arbitrary interconnect trees. For the small tree topology considered, we observe improvements of at least 18% in the accuracy of delay estimates when compared to the Elmore model (which is independent of inductance), even though our estimates are as easy to compute as the Elmore delay. The speedup of delay estimation via our analytical model is several orders of magnitude when compared to a simulation methodology such as SPICE
Keywords
VLSI; delays; distributed parameter networks; inductance; integrated circuit interconnections; integrated circuit layout; integrated circuit modelling; transmission line theory; RLC interconnects; VLSI interconnection lines; analytical delay model; delay estimation; inductance effects; interconnect trees; source-sink delays; Analytical models; Computational modeling; Delay effects; Delay estimation; Impedance; Inductance; Routing; SPICE; Topology; Transfer functions;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location
Atlanta, GA
Print_ISBN
0-7803-3073-0
Type
conf
DOI
10.1109/ISCAS.1996.541944
Filename
541944
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