New MPEG2 decoder architecture using frequency scaling

Author

Kim, Jeong-Min ; Chae, Soo-Ik

Author_Institution

Dept. of Electron. Eng., Seoul Nat. Univ., South Korea

Volume

4

fYear

1996

fDate

12-15 May 1996

Firstpage

253

Abstract

In this paper, we present a new clocking scheme in digital systems, called frequency scaling. It makes the system clock adjust to the lowest possible level, while maintaining the minimal processing capability for the current work-load. Therefore, the data-dependent algorithm, which requires simpler hardware and lower power consumption than the data-independent algorithm, can be used in real-time applications. We applied frequency scaling to two key function blocks of the MPEG2 decoder, that is VLD and IQ-IDCT, which have work-load with large variance in time

Keywords

VLSI; data compression; decoding; digital signal processing chips; discrete cosine transforms; real-time systems; timing; video coding; IQ-IDCT; MPEG2 decoder architecture; VLD; clocking scheme; data-dependent algorithm; digital systems; frequency scaling; inverse DCT; inverse quantisation IDCT; real-time applications; variable length decoder; Clocks; Control systems; Decoding; Digital systems; Energy consumption; Frequency; Hardware; Maintenance engineering; Resource management; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on

Conference_Location

Atlanta, GA

Print_ISBN

0-7803-3073-0

Type

conf

DOI

10.1109/ISCAS.1996.541950

Filename

541950