A new design approach and VLSI implementations of recursive digital filters

In this paper we address the design problem of high speed recursive digital filters for real time applications. In contrast to the nonrecursive case, there exist feedback loops in recursive filters which often become the performance bottleneck and prevent the circuits from high speed operation. Design tactics such as pipelining and parallel processing offer little help in this case. To achieve more parallelism, a look-ahead transformation applied at the algorithm level may be employed. This however, often causes a drastic increase in the hardware complexity. In this paper we propose a new design approach based on Distributed Arithmetic (DA) for the recursive filters. It can outperform the traditional bit parallel design in both pipelining period and initiation interval. To illustrate this new approach, we present 2 different systolic array designs for the ARMA filter. Finally, both designs are implemented by 0.8 μm SPDM CMOS technology. For the 4-tap 8-bit wide designs, the simulation results show they can operate at 142.6 and 142.8 MHz, respectively