Title :
Synthesis of testable PLAs using adaptive heuristics for efficiency
Author :
Bose, Pradip ; Bandyopadhyay, Subir ; Majumder, D. Dutta
Abstract :
The problem of integrating testability issues into the synthesis process of programmable-logic-array (PLA-)based VLSI logic design is investigated. Based on the insight gained from prior work on algorithmic and heuristic test generation for PLAs, a systematic methodology for synthesizing easily testable PLAs from high-level (Boolean) specifications is developed. Experimental results are presented to illustrate how adaptive heuristics aid in reducing the complexity of the synthesis-for-testability problem
Keywords :
VLSI; automatic testing; logic arrays; VLSI logic design; adaptive heuristics; complexity; heuristic test generation; programmable-logic-array; testability; testable PLAs; Automatic testing; Circuit faults; Circuit synthesis; Circuit testing; Design for testability; Electronic equipment testing; Logic design; Logic testing; Programmable logic arrays; System testing;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings, 1990 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-2079-X
DOI :
10.1109/ICCD.1990.130176
