Parallel implementation of medium level algorithms on a monolithic ASIMD multiprocessor

Author

Kneip, Johannes ; Ohmacht, Martin ; Wittenburg, Jens Peter ; Pirsch, Peter

Author_Institution

Lasb. fur Inf., Hannover Univ., Germany

Volume

4

fYear

1996

fDate

12-15 May 1996

Firstpage

316

Abstract

The efficient implementation of algorithms with irregular data access or control-flow on a parallel SIMD processor requires specific architectural measures. This paper demonstrates the parallelization of medium-level algorithms on the HiPAR-DSP, a programmable RISC processor for real-time image processing with 4 or 16 parallel data paths. We show the efficient use of memory and ASIMD control capabilities of the processor for the parallel execution of a memory efficient Huffman decoding algorithm. Performance figures for a selection of further medium level algorithms are given, demonstrating that even a SIMD architecture can obtain high utilization for algorithms with data dependent control flow

Keywords

Huffman codes; digital signal processing chips; image coding; image processing; multiprocessing systems; parallel architectures; parallel machines; real-time systems; HiPAR-DSP; SIMD architecture; data dependent control flow; irregular data access; medium level algorithms; memory efficient Huffman decoding algorithm; monolithic ASIMD multiprocessor; parallel SIMD processor; parallel data paths; parallel implementation; parallelization; programmable RISC processor; real-time image processing; Concurrent computing; Decoding; Electronic mail; Fluid flow measurement; Image processing; Performance evaluation; Reduced instruction set computing; Shape; Testing; VLIW;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on

Conference_Location

Atlanta, GA

Print_ISBN

0-7803-3073-0

Type

conf

DOI

10.1109/ISCAS.1996.541965

Filename

541965