Title :
Low-latency area-delay-efficient systolic multiplier over GF(2m) for a wider class of trinomials using parallel register sharing
Author :
Xie, Jiafeng ; Meher, Pramod Kumar ; He, Jianjun
Author_Institution :
Sch. of Inf. Sci. & Eng., Central South Univ., Changsha, China
Abstract :
Systolic structures for finite field multiplication involve large number of registers for parallel implementation, while bit-serial implementations require a large computation time, which increases along with the order of the field. In this paper, we present a novel scheme for the decomposition of the multiplication over GF(2m) based on irreducible trinomials into several independent units that facilitates maximal resister sharing and low-latency parallel implementation. It is shown that the proposed design involves significantly less area-delay complexity compared with the best of the corresponding existing systolic designs, and could be used for a wider class of trinomials.
Keywords :
Galois fields; circuit complexity; multiplying circuits; systolic arrays; GF(2m); area-delay complexity; bit-serial implementation; computation time; finite field multiplication; irreducible trinomials; low-latency area-delay-efficient systolic multiplier; low-latency parallel implementation; parallel register sharing; systolic design; systolic structure; Complexity theory; Computer architecture; Delay; Logic gates; Microprocessors; Polynomials; Registers;
Conference_Titel :
Circuits and Systems (ISCAS), 2012 IEEE International Symposium on
Conference_Location :
Seoul
Print_ISBN :
978-1-4673-0218-0
DOI :
10.1109/ISCAS.2012.6272184