Flexible L1 cache optimization for a low power embedded system

Large power consumption of memory access has been one of the major bottlenecks in modern embedded systems. Because caches even take about half of those systems´ power consumption. So it is essential in concentrating on optimized strategies for cache´s parameters as well as the enhancement of its adaptability to various applications. Considering the particular applications of embedded systems, we can optimize the caches with configuration parameters such as cache size, line size or associativity. In this paper, we firstly put forward the relations between those cache parameters, and the quantified results establish a new reconfigurable cache structure so as to find the optimal cache parameters rapidly by a searching algorithm. Furthermore, the possible hardware implementation with certain parameters is described, and the effectiveness of this method is verified by experiments using CACTI6.5 and SPEC2006 benchmark on Simple-scalar 3.0e. Experimental results show that the proposed cache can reduce the power consumption to 38.4% of its maximum power consumption caused by the redundant hardware resources.