Design of bi-directional bus nets

This paper shows the application of bi-directional bus in a reconfigurable communication chip. Based on author´s knowledge, there is very little research has been done on the bi-directional interconnect inside the chip due to limited applications. This paper formulates the design objective and timing constraints for the physical implementation. Then we discuss the optimization techniques including the wire sizing and clustering of tri-state buffers. These techniques have been applied in the 128-bit bi-directional roadrunner data bus design for this reconfigurable communication chip. The implementation details and other design issues such as the metal line self-heating and place & route CAD flow are also discussed in the paper.