Title :
A pMOS-based double-ladder integrated charge pump for standard process
Author :
Bazzini, Andrea ; Liu, Jingqi ; Gregori, Stefano
Author_Institution :
Sch. of Eng., Univ. of Guelph, Guelph, ON, Canada
Abstract :
A double-ladder pMOS charge pump circuit is proposed in this paper. It requires two phases (and their complements), CMOS standard process, without triple well. With this configuration an output voltage of 10.88 V can be reached with capacitive load, while every device (transistors and capacitors) sustain a maximum voltage not higher than VDD. Taking parasitic capacitances into account, the proposed structure can reach a 93% voltage boosting efficiency and a 52% power efficiency.
Keywords :
CMOS integrated circuits; capacitance; charge pump circuits; CMOS standard process; capacitive load; double ladder pMOS charge pump circuit; pMOS-based double ladder integrated charge pump; parasitic capacitance; power efficiency; voltage 10.88 V; voltage boosting efficiency; Boosting; Capacitance; Capacitors; Charge pumps; Integrated circuit modeling; Standards; Transistors;
Conference_Titel :
Circuits and Systems (ISCAS), 2012 IEEE International Symposium on
Conference_Location :
Seoul
Print_ISBN :
978-1-4673-0218-0
DOI :
10.1109/ISCAS.2012.6272204
