DocumentCode
3028408
Title
Using Pcache to Speedup Interpretation in Dynamic Binary Translation
Author
Chen, Wei ; Lu, Hongyi ; Shen, Li ; Wang, Zhiying ; Xiao, Nong
Author_Institution
Sch. of Comput., Nat. Univ. of Defense Technol., Changsha, China
fYear
2009
fDate
10-12 Aug. 2009
Firstpage
525
Lastpage
530
Abstract
Abstract- Dynamic binary translation (DBT) converts codes written for a source instruction set architecture (ISA) into optimized code for a target ISA. DBT has emerged as an important tool with real world applications. Interpretation is always adopted to handle the non hotspot code in a two stage DBT system. An important consideration in such DBT systems is the interpretation overhead. We investigate that repeated redecoding operations are the bottleneck of interpretation overhead. We propose interpreted code cache (Pcache), a hardware assist to save the information of the decoded instruction for reuse. We analyze and model Pcache performance via simulation on a DBT system simulator. Results from SPEC2000 integer benchmarks show that Pcache could significantly reduce redecoding operations and the overhead of interpretation in a DBT system. The speedup of interpretation is up to 17.12 on average with assist of Pcache. We also analyze the extra overhead caused by Pcache, which is neglectable compared to the performance gains.
Keywords
cache storage; codes; decoding; instruction sets; DBT; ISA; Pcache; SPEC2000; dynamic binary translation; instruction set architecture; interpreted code cache; Analytical models; Application software; Cost function; Decoding; Distributed processing; Emulation; Hardware; Instruction sets; Performance analysis; Performance gain; SPEC2000 benchmark; cache; dynamic binary translation; interpretation; simulator;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel and Distributed Processing with Applications, 2009 IEEE International Symposium on
Conference_Location
Chengdu
Print_ISBN
978-0-7695-3747-4
Type
conf
DOI
10.1109/ISPA.2009.83
Filename
5207885
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