Title :
Estimating aliasing in CA and LFSR based signature registers
Author :
Miller, D.M. ; Zhang, S. ; Pries, W. ; McLeod, R.D.
Author_Institution :
Dept. of Comput. Sci., Victoria Univ., BC, Canada
Abstract :
Aliasing estimations for cellular automata (CA) and linear feedback shift registers (LFSR) data compactors are presented. As data compaction is a heavily relied on technique for built-in self-test (BIST) the results should be of practical, as well as theoretical interest. Aliasing estimation techniques for multiple-input data compactors are considered. In particular, exact and approximate computation techniques are developed and discussed for CA and LFSR registers. Aliasing estimates for CA and LFSR structures are provided for the ISCAS-85 benchmark circuits for single stuck-at and single delay faults
Keywords :
built-in self test; finite automata; integrated circuit testing; logic testing; shift registers; ISCAS-85 benchmark circuits; aliasing estimate; built-in self-test; cellular automata; data compactors; linear feedback shift registers; multiple-input data compactors; single delay faults; single stuck at faults; Benchmark testing; Built-in self-test; Circuit faults; Circuit testing; Compaction; Computer science; Delay estimation; Feedback circuits; Linear feedback shift registers; Test pattern generators;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings, 1990 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-2079-X
DOI :
10.1109/ICCD.1990.130189
