HAL III: function level hardware logic simulation

Author

Takasaki, Shigeru ; Nomizu, Nobuyoshi ; Hirabayash, Yoshihiro ; Ishikura, Hiroshi ; Kurashita, Masahiro ; Koike, Nobuhiko ; Nakata, Toshiyuki

Author_Institution

NEC Corp., Tokyo, Japan

fYear

1990

fDate

17-19 Sep 1990

Firstpage

167

Lastpage

170

Abstract

A function-level hardware simulator, HAL III, is described. HAL III can simulate a circuit model written by a register transfer level language FDL without translating it into gate level. It adopts parallel, pipeline, and flexible FDL evaluation architectures, and uses level sort and event-driven algorithms at register transfer level. HAL III is more than 10000 times faster than conventional gate-level software simulators in the case of 31 processors used. HAL III can be expanded to 127 processors. HAL III can also be used as a fault simulator. Its simulation speed can be estimated more than a hundred times faster than software simulators. HAL III has been successfully used in practical VLSI designs

Keywords

VLSI; circuit analysis computing; digital simulation; logic design; HAL III; VLSI designs; circuit model; function level hardware logic simulation; register transfer level language FDL; simulation speed; Circuit simulation; Cities and towns; Computer architecture; Design methodology; Hardware; Logic design; National electric code; Registers; Supercomputers; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings, 1990 IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-2079-X

Type

conf

DOI

10.1109/ICCD.1990.130192

Filename

130192