A fast and area-efficient VLSI architecture for embedded image coding

We propose a VLSI architecture for an embedded zerotree wavelet (EZW) algorithm. Our partitioning and mapping of the computations leads to parallel operations of independent processors and balances the workload. Our data mapping technique simplifies the memory access and the processor architecture. The resulting architecture is area-efficient and can be used to design a low-power system for mobile/visual communication applications. A video codec based on the parallel architecture can simultaneously handle multiple video channels of various resolutions