Title :
Development of a VLSI chip for real time MPEG-2 video decoder
Author :
Morimatsu, Eishi ; Sakai, Kiyoshi ; Yamashita, Koichi ; Ohta, Mitsuhiko ; Miyasaka, Hideki ; Maeda, Kiyoshi ; Ogura, Hisakazu ; Takeshita, Naoyuki
Author_Institution :
Fujitsu Labs. Ltd., Kawasaki, Japan
Abstract :
A VLSI chip fully compatible with ISO/IEC 13818 2 (MPEG-2 video) has been developed. The chip is conforming to main profile @ main level of the standard, which realizes real-time decoding of ITU-R Rec.601 format moving pictures. In addition, it is also designed to operate as a part of MPEG-2 encoder. The chip size and power dissipation are minimized by optimizing its architecture and by using hardware macro cells for bulky circuits such as multipliers. As a result, the chip has been implemented with approximately 620K transistors on 11.35×11.35 mm using a triple metal 0.5 μm CMOS technology. The chip has performed well in evaluations on a PC-based testbed
Keywords :
CMOS digital integrated circuits; ISO standards; VLSI; circuit optimisation; decoding; digital signal processing chips; real-time systems; telecommunication standards; video coding; video signal processing; 0.5 micron; 11.35 mm; CMOS technology; ISO/IEC 13818 2; ITU-R Rec.601 format moving pictures; MPEG-2 encoder; VLSI chip; architecture; bulky circuits; chip size; hardware macro cells; main profile @ main level; multipliers; power dissipation; real time MPEG-2 video decoder; transistors; Circuits; Decoding; Discrete cosine transforms; IEC standards; ISO standards; Laboratories; Petroleum; Very large scale integration; Video codecs;
Conference_Titel :
Image Processing, 1995. Proceedings., International Conference on
Conference_Location :
Washington, DC
Print_ISBN :
0-8186-7310-9
DOI :
10.1109/ICIP.1995.537670
