Automated behavioral testing of VHDL components

Design reuse is essential for dealing with complex integrated circuits and printed circuit boards. The use of a hardware description language such as VHDL is becoming a requirement for this kind of reuse. The current practice is to model the design component in VHDL and to test the design´s behavior using a testbench, which applies test cases and reports deviations of actual behavior from expected behavior. In this paper we present VHDLGEN, a prototype method and tool for algorithmic testing of VHDL designs, adapted from a successful approach to testing software components. Testing with VHDLGEN involves a special interface to the component under test, a scripting language, and a driver generator. VHDLGEN is oriented towards highly automated testing, where the driver generates the inputs, runs the tests, and checks the outputs for correctness. We present evidence that the VHDLGEN approach is feasible. Our experience with algorithmic testing of software components suggests that VHDLGEN will scale up to more complex designs and will be adaptable to designs in object-oriented HDLs as they become available