DocumentCode
3030275
Title
A low power 5 MS/s 14 bit switched capacitors digital to analog converter
Author
Gallin-Martel, L. ; Dzahini, D. ; Rarbi, F. ; Rossetto, O.
Author_Institution
LPSC, UJF, Grenoble, France
fYear
2010
fDate
2-4 June 2010
Firstpage
240
Lastpage
243
Abstract
The ILC ECAL front-end chip will integrate many functions of the readout electronics including a DAC dedicated to the calibration. We present a 14 bit DAC, designed in a CMOS 0.35 μm process and based on segmented arrays of switched capacitors controlled by a Dynamic Element Matching (DEM) algorithm. This DAC features an INL lower than 0.5 LSB at 5 MHz, and dissipates less than 7 mW.
Keywords
CMOS integrated circuits; digital-analogue conversion; readout electronics; switched capacitor networks; 14 bit switched capacitors; CMOS process; ILC ECAL front-end chip; digital to analog converter; dynamic element matching algorithm; readout electronics; size 0.35 mum; word length 14 bit; CMOS process; Calibration; Capacitors; Digital-analog conversion; Indium phosphide; Linearity; Network topology; Noise cancellation; Noise reduction; Readout electronics; Digital to analog converter; dynamic element matching; switched capacitors;
fLanguage
English
Publisher
ieee
Conference_Titel
IC Design and Technology (ICICDT), 2010 IEEE International Conference on
Conference_Location
Grenoble
Print_ISBN
978-1-4244-5773-1
Type
conf
DOI
10.1109/ICICDT.2010.5510251
Filename
5510251
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