VLSI implementations of the triple-DES block cipher

In this paper, VLSI implementations for the triple-DES block cipher are presented. Triple-DES (TDES) is basically used in various cryptographic applications and wireless protocol security layers. Three different hardware implementations are proposed. The first two are based on the pipeline technique, while the third uses consecutive iterations for the data transformations. In addition, the used TDES S-BOXes has been implemented by both look up tables (LUT) and ROM blocks providing useful information regarding the covered area and the design throughput. The ROM approach has better performance than the LUT one but the latter is preferred in the cases where ROM blocks are not available. The proposed TDES implementations achieve high-speed performance. In particular, the throughput value for the pipeline one is equal to 7.36 Gbps.