Design and analysis of Toffoli gate using adiabatic technique

This paper presents the comparison of two efficient adiabatic logics ECRL and PFAL. A Toffoli gate is implemented using these two design technique. Toffoli gate is one of reversible gate. Reversible computing performed on Toffoli gate with adiabatic design techniques promises more reduced in power consumption as compared to traditional adiabatic CMOS circuits. Comparison in this paper shows very encouraging results in terms of average power consumption, delay, transistor count. The designs are simulated and implemented on Cadence ICE6.1.5 virtuoso Design Environment using UMC 180 nm transistor model. The simulation results indicate that ECRL is better than PFAL adiabatic logic at lower value load capacitance in terms of average power consumption and transistor count for implementation of Toffoli gate at low frequency and low power application.