Title :
A robust latch-type sense amplifier using adaptive latch resistance
Author :
Song, Taejoong ; Lee, Sang Min ; Choi, Jaehyouk ; Kim, Stephen ; Kim, Gyuhong ; Lim, Kyutae ; Laskar, Joy
Author_Institution :
ECE Dept., Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
A latch-type sense amplifier (SA) utilizing adaptive resistance technique is proposed. With adaptively adjusted resistance in a latch path, the proposed SA can compensate for an erroneous voltage drop in bit-lines induced by bit-cell leakage current. The simulation shows that the sense amplifier margin (SM) is improved in the presence of mismatches. The SA test chip is fabricated in a 0.18-μm CMOS technology showing the SM improvement of 6% to 15% at various supply voltages.
Keywords :
CMOS memory circuits; SRAM chips; amplifiers; electric potential; electric resistance; flip-flops; integrated circuit testing; leakage currents; CMOS technology; SA test chip; SRAM; adaptive latch resistance; bit-cell leakage current; bit-lines; erroneous voltage drop; latch path; latch-type sense amplifier; sense amplifier margin; size 0.18 mum; supply voltage; CMOS technology; Degradation; Leakage current; Logic; Random access memory; Robustness; SRAM chips; Samarium; Testing; Voltage control; SRAM; bit-cell; latch sense amplifier; leakage current;
Conference_Titel :
IC Design and Technology (ICICDT), 2010 IEEE International Conference on
Conference_Location :
Grenoble
Print_ISBN :
978-1-4244-5773-1
DOI :
10.1109/ICICDT.2010.5510258
