Low power conditional pulse control with Transmission Gate Flip-Flop

Author

Berwal, Deepak ; Kumar, Ashish ; Kumar, Yogendera

Author_Institution

VLSI Div., Galgotias Univ., Greater Noida, India

fYear

2015

fDate

15-16 May 2015

Firstpage

1358

Lastpage

1362

Abstract

In the present work, Low Power Conditional Pulse Control with Transmission Gate Flip-Flop (CPCTG-FF) design based on signal feed through scheme is proposed. The proposed design removes the long discharging path problem with intermediate nodes using the pulse generation control logic with transmission gate (which facilitates a faster discharge operation). Transmission gate and a NMOS are used to control the input data and clock circuit to reduce the power dissipation along the critical path. As a result, very low power dissipation occurs when there is no switching. T-Spice (Tanner 14.1) is used for the simulation purposes. All simulation results are based on using CMOS 90-nm technology at 500MHz clock frequency. Its maximum power saving compared to conditional pulse enhancement scheme flip-flop [1] is up to 16.84% and compared to signal feed through scheme designs [2] is up to 37.19%.

Keywords

CMOS logic circuits; MOS integrated circuits; flip-flops; logic design; low-power electronics; pulse generators; sampled data systems; CMOS technology; CPCTG-FF design; NMOS; T-Spice; clock circuit; clock frequency; conditional pulse enhancement scheme flip-flop; data circuit; frequency 500 MHz; low power conditional pulse control; power dissipation; pulse generation control logic; signal feed through scheme; size 90 nm; transmission gate flip-flop; Clocks; Delays; Feeds; Flip-flops; Inverters; Logic gates; Transistors; Flip-Flops; conditional pulse; low power; transmission gate;

fLanguage

English

Publisher

ieee

Conference_Titel

Computing, Communication & Automation (ICCCA), 2015 International Conference on

Conference_Location

Noida

Print_ISBN

978-1-4799-8889-1

Type

conf

DOI

10.1109/CCAA.2015.7148589

Filename

7148589