Improving efficiency of power gated circuits through concurrent optimization of power switch size and forward body biasing

Power gating (PG) has emerged as an effective technique to reduce standby leakage power in portable devices where battery life time is vital. However, it comes at the cost of timing overhead which is a problem for most of the applications where real-time constraints exist. Designing efficient power gated circuits is very challenging problem due to contrasting requirements in active mode (low timing overhead implying larger power switch size) and standby mode (low standby leakage power implying smaller power switch size). In this work, we show that applying Forward Body Biasing (FBB) to the logic gates in conjunction with power gating (PG + FBB) will provide us with an additional degree of freedom which can be utilized to improve the efficiency of the power gated circuit. We propose an optimization algorithm to find the optimum power switch size and FBB value such that total leakage energy of the design (active + standby) in minimized. Results show that our PG + FBB technique on an average improves the leakage energy savings by 2X-5X as compared to using only power gating. With PG + FBB technique, one can also design a zero delay penalty power gated circuit which is not possible if only power gating is used.