Design of charge pump circuit in low-voltage CMOS process with suppressed return-back leakage current

Author

Weng, Yi-Hsin ; Tsai, Hui-Wen ; Ker, Ming-Dou

Author_Institution

Inst. of Electron., Nat. Chiao-Tung Univ., Hsinchu, Taiwan

fYear

2010

fDate

2-4 June 2010

Firstpage

155

Lastpage

158

Abstract

A new charge pump circuit has been proposed to suppress the return-back leakage current without suffering the gate-oxide overstress problem in low-voltage CMOS process. A test chip has been implemented in a 65-nm CMOS process to verify the proposed charge pump circuit with four pumping stages. The measured output voltage is around 8.8 V with 1.8-V supply voltage, which is better than the conventional charge pump circuit with the same pumping stages. By reducing the return-back leakage current and without suffering gate-oxide reliability problem, the new proposed charge pump circuit is suitable for the applications in low-voltage CMOS IC products.

Keywords

CMOS integrated circuits; charge pump circuits; integrated circuit reliability; low-power electronics; charge pump circuit; gate-oxide reliability problem; low-voltage CMOS process; size 65 nm; suppressed return-back leakage current; voltage 1.8 V; Application specific integrated circuits; CMOS integrated circuits; CMOS process; Charge measurement; Charge pumps; Circuit testing; Current measurement; Leakage current; Semiconductor device measurement; Voltage measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

IC Design and Technology (ICICDT), 2010 IEEE International Conference on

Conference_Location

Grenoble

Print_ISBN

978-1-4244-5773-1

Type

conf

DOI

10.1109/ICICDT.2010.5510271

Filename

5510271